In the flash EEPROM (Electrically Erasable Programmable Read Only Memories) including split gate FET devices, the level of voltage in the respective gate electrodes and tunneling current through respective insulating layers is frequently dependent on gate electrode profiles. For example, Fowler-Nordheim tunneling has an exponential field dependence and the electric field produced at electrode interfaces can be strongly affected by electrode profiles.
A recurring processing problem in forming EEPROM devices, is the tendency for polysilicon residual material to form in undesired areas of the memory cell, including non-active areas during Reactive ion etch (RIE) processes. RIE etch processes are increasingly used for etching the various polysilicon electrodes in EEPROM flash memory devices for example in self-aligned stacked configurations.
For example, in a particular type of EEPROM flash memory cell, a triple poly split gate configuration is utilized where each memory cell has four terminals including source, drain, select gate, and control gate. The selection of a particular memory cell for programming is dependent only on the voltage applied to the particular select gate and the particular source. Consequently, this permits a variable amount of voltage to be applied to the control gate during programming, which controls the amount of electrons injected onto the floating gate. Thus, more than one level of charge may be stored on the floating gate of each memory cell.
In the formation of polysilicon floating gate and control electrodes in a triple poly split gate configuration, a consistent and predictable profile of the polysilicon structure including the absence of residual polysilicon is critical to proper electrical functioning of the device. As design rules have decreased, achieving acceptable etching profiles of the polysilicon structures has become increasingly difficult due to several hard to control RIE etching phenomena including polysilicon residue formation and micro-trenching as a result of secondary plasma ion bombardment. In addition, problems are presented in RIE etching processes where different doping levels of polysilicon layers and polysilicon layer surface topography cause variable etching rates. In particular in the triple poly split gate configuration, using three layers of polysilicon, the variable topography of the polysilicon layers tends to cause undesirable etching phenomenon due to etching at different rates through different materials at particular points in the etching process thereby contributing to the undesired deposition of etching residues. The undesired etching residues including polysilicon residues tend to form on gate profiles thereby altering electric fields and consequent electron tunneling behavior as well as forming on active and non-active areas of a memory cell matrix thereby reducing yield and reliability of the memory cell matrix.
There is therefore a need in the EEPROM device processing art to develop improved etching processes to improve the etching profiles of gate electrode structures while reducing etching residues including triple-poly split gate configuration memory cells to thereby improve the yield and reliable operation of split gate flash memory devices.
It is therefore an object of the invention to provide improved etching profiles of gate electrode structures while reducing etching residues including triple-poly split gate configuration memory cells to thereby improve the yield and reliable operation of split gate flash memory devices, while overcoming other deficiencies and shortcomings of the prior art.